module ysyx_22040213_inDataSel(
//	input imm_en,
	input [3:0] AluData1_en,
	input [6:0] AluData2_en,
//	input jump_en,
//	input jumpr_en,
//	input shiftimm_en,
	input [63:0] src1,
	input [63:0] src2,
	input [63:0] ext_imm,
	input [63:0] pc,
	input [63:0] shamt,


	output [63:0 ]data1,
	output [63:0] data2
);
	//assign data2 = imm_en? ext_imm : src2;
//	assign data1 = pc_en? pc : src1;
//	assign data2 = jump_en||jumpr_en ? 64'b0100 :(imm_en? (shiftimm_en ? shamt: ext_imm) : (shiftimm_en ? shamt: src2));	 
	wire [63:0] pc_sub_4;
	assign pc_sub_4 = pc - 4;
	MuxKey #(4, 4, 64) i0 (data1, AluData1_en, {
		4'b1000, pc_sub_4,
		4'b0100, {{32{src1[31]}},{src1[31:0]}}, //sraw
		4'b0010, {{32{1'b0}},{src1[31:0]}}, //srliw
		4'b0001, src1
		});

	MuxKey #(7, 7, 64) i1 (data2, AluData2_en, {
		7'b1000000, {{32{1'b0}},{src2[31:0]}},
		7'b0100000, {{32{src2[31]}},{src2[31:0]}},
		7'b0010000, 64'b0100,
		7'b0001000, shamt,
		7'b0000100, ext_imm,
		7'b0000010, shamt, 
		7'b0000001, src2
		});

endmodule
